For some fifteen years, two-dimensional semiconductors just one atomic sheet thick have promised transistors smaller and more frugal than silicon — while almost never meeting both goals at once: thin the gate dielectric to command the channel better or preserve electron mobility, but not both. A Taiwanese team led by National Yang Ming Chiao Tung University (NYCU) and TSMC Corporate Research — with National Taiwan University, Academia Sinica and the National Applied Research Laboratories — has just sidestepped that trade-off by working neither on the semiconductor nor on the dielectric, but on the few-atom layer that separates them. What changes: the interface stops being a boundary one puts up with and becomes a functional part of the transistor.

Source: nature.com

In plain terms

A transistor is an electrical switch commanded by a "gate"; between the gate and the channel where the electrons flow, a thin insulating layer is needed. The thinner that layer, the better the gate controls the current — like a finger pressing on a soft tube through a piece of cloth: the thinner the cloth, the more precise the control. But on a material as smooth as a sheet three atoms thick, depositing this very thin insulator damages it and slows the electrons down. The researchers slipped in a buffer barely half a billionth of a metre thick — obtained by oxidising an aluminium film — which smooths the surface for the insulator while protecting the flow of electrons. The result: a very thin insulator and good performance, on a material (molybdenum disulfide) made by a method compatible with mass production. This is not yet a commercial chip: it is a laboratory demonstration, and scaling up to industry remains to be done.

Technical sheet — Discovery

Technical explanation

1. Why the gate insulator is the bottleneck. A MOSFET modulates the channel current through the field applied across a gate dielectric. The quality of electrostatic control comes down to a single quantity, the equivalent oxide thickness (EOT): $\mathrm{EOT} = t_{\text{diel}} \times \dfrac{\kappa_{\mathrm{SiO_2}}}{\kappa_{\text{diel}}}$EOT=tdiel​×κdiel​κSiO2​​​, where $t_{\text{diel}}$tdiel​ is the physical thickness and $\kappa$κ the relative permittivity. The lower the EOT, the more tightly the gate "grips" the channel and the shorter the transistor can be without leaking. Using a high-κ dielectric such as HfO₂ ($\kappa \approx 20\text{–}25$κ≈20–25, versus $\approx 3{,}9$≈3,9 for SiO₂) allows, at a given EOT, a greater physical thickness to be retained — hence less tunnelling current. Reaching an EOT ≈ 1 nm here on a monolayer is the control performance being sought.

2. The specific problem of 2D: a surface that is too perfect. Monolayer MoS₂ has no dangling bonds at its surface (it is terminated by saturated sulfur atoms, interacting by van der Waals forces). This chemical perfection, which underlies its mobility, hampers standard deposition techniques (ALD in particular) in nucleating a thin, continuous film: the oxide grows in islands, leaves holes, and creates interface defects and electrostatic disorder. That disorder scatters the carriers and wipes out the mobility gain one came to 2D for. Hence the trade-off endured so far: good gate control or good mobility, rarely both.

3. The buffer's two roles, as the authors describe them. The team first deposits an epitaxial layer of metallic aluminium directly on the MoS₂ monolayer, then oxidises it in a controlled way to form an Al₂O₃ roughly 0.42 nm thick — barely one to two atomic planes. This buffer plays two physically distinct roles. First, it offers a smooth, continuous surface on which the HfO₂ can grow uniformly: the buffer solves the nucleation problem in place of the MoS₂. Second, it suppresses dielectric-induced scattering: the article's abstract states, in substance, that this layer enables uniform integration of the hafnium oxide and suppresses dielectric-induced scattering, yielding strong gate control without notable mobility degradation (rendered from the French edition of this bulletin, not quoted verbatim from the published abstract). This is the mechanism claimed by the authors themselves, and it bears on the exact cause of the trade-off described above. The NYCU press release gives a popularised version of it — an "atomic buffer" that limits parasitic electrical interactions between the dielectric and the semiconductor. (Editorial clarification, not attributed to the study: among the known mechanisms of this scattering are interface trapped charges and surface polar phonons of the high-κ; the source does not specify which dominates here, the full text not having been consulted.) The interface therefore does not merely separate two materials: it serves both as a growth surface for the HfO₂ and as a layer that suppresses dielectric-induced scattering, while transmitting the gate field.

4. What the methods prove — and how. The argument rests on real transistors, not on a simulation.

   • The choice of MoS₂ grown by CVD (rather than mechanically exfoliated) is methodologically decisive: exfoliated flakes yield handsome laboratory records but cannot be manufactured at wafer scale. Demonstrating the method on CVD monolayer means showing that it applies to the material that is a candidate for industrialisation, not to an ideal case.
   • The measurement of transconductance $g_m = \partial I_D / \partial V_G$gm​=∂ID​/∂VG​ (here 0.45 mS·µm⁻¹) directly quantifies the efficiency of the command: a high $g_m$gm​ at a channel length of ≈ 100 nm demonstrates that the gate strongly drives the current. Combined with an EOT ≈ 1 nm, it establishes the intended electrostatic control.
   • The low leakage current indicates that, despite the thinness, buffer + HfO₂ still insulates (no prohibitive tunnelling); the minimal hysteresis suggests a low trap density at the interface. On the decisive point — carrier transport — the authors conclude in their abstract that there is strong gate control without notable mobility degradation: this is the study's central claim, the one that marks the lifting of the trade-off. It nevertheless remains qualitative in what was consulted: neither a mobility value nor a quantified trap density appears in the abstract or in the press release.

Why It Worked

The lever is neither a new semiconductor nor a new dielectric, but the engineering of the boundary between the two. Earlier approaches — other dielectrics, molecular seeding layers, alternative oxide deposition methods — had only rarely combined low EOT with preserved carrier transport, particularly on CVD-grown monolayer MoS₂. The explanation advanced for the 0.42 nm Al₂O₃ buffer is that it acts on the common cause — poor nucleation and interface disorder — rather than on its symptoms.

The gap between what is demonstrated and what is announced must remain explicit. What the study establishes: short-channel top-gate transistors, in CVD MoS₂, reaching EOT ≈ 1 nm and $g_m$gm​ = 0.45 mS·µm⁻¹ with low leakage and hysteresis. What remains to be done, and what the authors state themselves: optimising the process for large-scale manufacturing. This is a proof of concept at the device level, not a technology qualified for production — a distinction that, on the maturity scale of hard engineering, separates a test bench from an industrial node.

Causal Chain

End of silicon scaling → search for ultrathin channels → 2D semiconductors (MoS₂ monolayer, ≈ 0.65 nm, high mobility in the 2D regime) → need for a low-EOT gate dielectric to command short channels → van der Waals surface with no dangling bonds → non-uniform nucleation of a thin oxide → islands, defects, interface disorder → carrier scattering, mobility loss → historical trade-off control vs mobility → oxidised epitaxial Al buffer (Al₂O₃ ≈ 0.42 nm) → uniform HfO₂ nucleation + suppression of dielectric-induced scattering → EOT ≈ 1 nm with $g_m$gm​ = 0.45 mS·µm⁻¹, low leakage, low hysteresis → demonstration on CVD monolayer → (horizon) candidate building block for low-power "beyond silicon" logic.

Anecdote

Molybdenum disulfide is not an exotic laboratory material: it is the grey-black dry lubricant of the workshop, long prized because its sheets slide over one another — the same absence of bonds between planes that today both gives monolayer MoS₂ its mobility and makes it so hard to attach an oxide to it. The property that made it a good lubricant is exactly the one that complicates its transformation into a transistor.

Legacy and Current Data

The industrial stake is the extension of Moore's law. 2D semiconductors are regularly presented as candidate channels for the most advanced nodes, precisely where ultrathin silicon loses its mobility. The presence of TSMC Corporate Research among the authors places the work on an industrialisation trajectory rather than in academic curiosity. That said, the published result remains upstream of production: an individual device demonstrated, not a wafer yield or a circuit integration. What remains to be established — repeatability, uniformity across a full wafer, reliability over time, compatibility with the manufacturing flow — is not quantified here and conditions any scaling up; the authors themselves state only that the process still needs to be optimised for large-scale manufacturing.

The researcher's view — open questions

(Interpretation, not results of the study.) The decisive experiments that would extend this work: (1) a uniformity mapping of EOT and $g_m$gm​ across a full wafer, to verify that the 0.42 nm buffer can be controlled at industrial scale and not only on selected devices; (2) a reliability test under prolonged voltage stress (threshold-voltage drift, dielectric breakdown), the classic Achilles' heel of ultrathin high-κ layers; (3) a portability test of the process to other 2D semiconductors (WS₂, WSe₂) and to complementary n/p architectures, a condition for building complete CMOS logic rather than an isolated transistor.

Sources

References verified during the fact-checking audit (accessed 10 August 2026).

• Su, Y.-C. et al. High-transconductance molybdenum disulfide top-gate transistors using epitaxial interface engineering. Nature Electronics, 2026. DOI: 10.1038/s41928-026-01672-7. (Peer-reviewed article — primary source. Public abstract consulted; full text, Methods and Results not consulted.)
• National Yang Ming Chiao Tung University. A 0.42-nanometer breakthrough could push transistors beyond silicon. Press release, relayed by ScienceDaily, 9 August 2026. sciencedaily.com (Press release from the authors' institution — cited for the channel length, the leakage and the hysteresis, as well as for the popularised description of the buffer's role.)

Background references

(Context for the general mechanism, distinct from the study's primary source.)

• Gong, X. et al. Two-Dimensional Semiconductor–Metal Contact Engineering: Challenges and Strategies for High-Performance Electronics. Advanced Functional Materials, 29 December 2025. DOI: 10.1002/adfm.202526021. (Review — it deals with metal/2D-semiconductor contacts, a neighbouring but distinct field from the gate interface treated here; cited for the general framework of 2D interfaces. The notions of EOT, high-κ and dangling bonds belong to standard microelectronics.)

---

Confidence statement. Solidly established: the fabrication of top-gate transistors in CVD monolayer MoS₂ incorporating an Al₂O₃ buffer ≈ 0.42 nm beneath a high-κ HfO₂, reaching an EOT ≈ 1 nm and a maximum transconductance of 0.45 mS·µm⁻¹ at a channel length of ≈ 100 nm, with low leakage and minimal hysteresis (measured result, primary source Nature Electronics, peer-reviewed). Transparency: the full text of the article (Methods/Results) was not consulted. The EOT ≈ 1 nm, the transconductance of 0.45 mS·µm⁻¹ and the mechanism (suppression of dielectric-induced scattering, without notable mobility degradation) are stated in the public abstract of the article; the channel length of ≈ 100 nm as well as the mentions of leakage and hysteresis come from the NYCU press release — each value is attributed to its source. No device figure has been added from memory; the context values not drawn from the source (κ of HfO₂ and of SiO₂, thickness of the MoS₂ monolayer, ALD nucleation mechanism, polar phonons) are textbook constants or mechanisms, flagged as such in the text. The absence of mobility degradation is asserted by the authors but not quantified in the sources consulted (neither a mobility value nor a trap density): the statements on carrier transport therefore remain qualitative, as do the authors'. Not yet established / outside the result: wafer-scale uniformity, reliability under stress, circuit integration and industrial feasibility, — the authors explicitly deferring to later work the optimisation of the process for large-scale manufacturing, the other reservations being the editorial team's reading (maturity level: laboratory prototype). Technical checks: DOI resolved; 21 authors, 5 institutions and three corresponding authors (Tsung-En Lee, Iuliana P. Radu, Wen-Hao Chang) verified on Crossref and OpenAlex; EOT formula and units consistent. Dates: published online on 31 July 2026 (Crossref/OpenAlex in agreement), first press pickups from 7 August 2026, ScienceDaily relay on 9 August — the gap is verified and made explicit in the technical sheet. Uniqueness verdict: UNIQUE — no close key in the registry (A001–A006); first article on the site covering 2D transistors / microelectronics.